1. Field
The present invention relates to timing circuits for interfaces between different semiconductor chips or components, and in particular to a delay locked loop for generating timing signals based on a received reference clock.
2. Related Art
To allow semiconductor devices to communicate at high speeds I/O (in put/output) links at each chip are used to drive data and clock pulses between the two components. In high performance semiconductor systems, the links may be a major factor in the operational speed of the system. The speed of such links may be very important of I/O links between a CPU (central processing unit) and an MCH (memory control hub), between a MCH and memory, between CPUs, between a CPU and memory, and for other chip-to-chip communications.
As microprocessor designs move toward higher speed I/O, low power and low jitter DLLs (delay locked loop) become more important. This may be particularly so when a DLL is used to generate a sampling clock at the center of the data eye. As data rates reach 6.4 GHz, the data eye width for receivers is about 70 ps. This reduces the margin for jitter and reducing the jitter increases the setup and hold time margin. Since chip performance may also be limited by power consumption and the heat produced, lower power circuits also allow for higher processing and I/O performance. As the number of DLLs increases, so does the impact of the power consumption of each DLL. A DDR2 (Double Data Rate 2) interface, for example, uses 108 master and slave DLLs to support the required bandwidth.
Currently two types of delay cell designs are used in high speed I/O links between semiconductor devices. One is the self-biased differential delay cells that are the building blocks of SBDLL (self-biased differential delay-locked loop), and a second is the current starved delay cell. A differential delay cell is basically a differential transistor pair with an NMOS (n-gate metal oxide semiconductor) current source and PMOS (p-gate metal oxide semiconductor) loads, where DC (direct current) current flows. When the low-swing differential waves in the delay chains are converted back to CMOS (Complementary Metal Oxide Semiconductor) signals for clock distributions, another 2-stage differential amplifier is required for each clock output tap. The differential amplifiers consume a significant amount of power and generate a corresponding significant amount of heat.
The jitter performance for SBDLL circuits is also limited by the low output impedance of the short channel transistors used. These transistors are poor current sources. Self-biased differential delay cells also produce duty cycle errors because of differential pair offset and output level shifter distortion.
In current starved delay cells, a p-bias (gate bias to a PMOS device) is generated by a current mirror (a PMOS device that is connected as a MOS diode). However if the pull-up strength and pull-down strength of the p-bias within the current mirror is not matched, the duty cycle of the output will be poorly formed and noise rejection in the power supply will also be poor.